Introduction to ARM Processor for JKSSB SI Telecommunication: Complete Exam Note

Where ARM Fits in the JKSSB SI Telecom Exam

Under the syllabus notified with Advertisement No. 11 of 2025, the written exam has 100 objective questions, 2 marks each, 120 minutes, with 0.5 negative marking. Part B (technical) carries 140 marks.

• Subject: Digital Electronics & Microprocessors (20 marks)
• Related topics in the same subject: number systems, logic gates, Boolean algebra, K-maps, flip-flops, counters, 8085/8086 architecture and interrupts, and the 8051 microcontroller
• ARM's share: it is listed as an introduction, so expect a handful of questions at most. They are usually direct facts: full form, RISC features, registers, modes, pipeline, Thumb and Cortex families.

1. What Is ARM?

ARM stands for Advanced RISC Machines. It was originally Acorn RISC Machine, named after Acorn Computers of Cambridge, UK, where the first ARM processor was designed in the mid-1980s.

• Architecture type: RISC (Reduced Instruction Set Computer), load/store architecture
• Word size: 32-bit registers and a 32-bit data path in classic and Cortex cores; 64-bit execution (AArch64) from ARMv8-A onwards
• Business model: Arm designs architectures and processor cores and licenses them to chip makers such as Qualcomm, Samsung, NXP and STMicroelectronics, who build the actual chips. This is called an IP-licensing model.
• Strengths: low power consumption, small silicon area, high performance per watt

Quick history

• 1985: first ARM silicon (ARM1) at Acorn
• 1987: ARM2 powers the Acorn Archimedes computer
• 1990: ARM Ltd formed as a joint venture of Acorn, Apple and VLSI Technology, and the name changes to Advanced RISC Machines
• 1990s: ARM7TDMI becomes hugely popular in mobile phones and embedded devices
• 2004 onwards: the Cortex family (A, R, M profiles) replaces the older numbered cores
• 2011 onwards: ARMv8 brings 64-bit computing; ARMv9 follows

2. RISC vs CISC

Remember: ARM is a RISC design but not "pure" RISC. It adds features such as conditional execution, a barrel shifter and load/store multiple instructions to improve code density and speed.

3. Key Features of the ARM Architecture

• Load/store architecture: data processing works only on registers. Memory is accessed with LDR and STR (and LDM/STM).
• Fixed-length instructions: 32 bits in ARM state, which simplifies decoding.
• Three-address instruction format: ADD R0, R1, R2 has two sources and one separate destination.
• Conditional execution: almost every ARM-state instruction has a 4-bit condition field, which avoids many branches.
• Barrel shifter: one operand can be shifted or rotated as part of the same instruction at no extra cycle cost.
• Flag control: the S suffix decides whether an instruction updates the condition flags.
• Load/store multiple: LDM and STM move several registers in one instruction.
• Thumb instruction set: a compressed 16-bit instruction set for better code density.
• Memory-mapped I/O only: ARM has no separate IN/OUT instructions like the 8085. Peripherals are accessed with ordinary load/store instructions.
• Enhanced debug: JTAG and Serial Wire Debug support.

4. ARM Architecture Versions and Cortex Families

Do not confuse the architecture version (the instruction set specification, such as ARMv7) with the core (an actual design, such as Cortex-M3).

The three Cortex profiles

• Cortex-A (Application): high-performance cores for smartphones, tablets, set-top boxes and servers. They run full operating systems such as Linux and Android and use a memory management unit (MMU).
• Cortex-R (Real-time): fast, deterministic response for hard disks, automotive braking systems and cellular baseband modems.
• Cortex-M (Microcontroller): low-cost, low-power cores for IoT devices, sensors, motor control and smart meters. This is the family you are most likely to meet in embedded and telecom questions.

5. ARM7TDMI Decoded

ARM7TDMI is the classic core used to teach ARM architecture, and exam questions often use its name.

• Architecture version: ARMv4T
• Data width: 32-bit
• Pipeline: 3 stages (fetch, decode, execute)
• Memory architecture: Von Neumann (single bus for instructions and data)
• Total registers: 37 (31 general-purpose 32-bit registers and 6 status registers)

6. Programmer's Model: Registers

In ARM state, 16 registers (R0 to R15) plus the CPSR are visible at any one time. Which physical register you see depends on the current processor mode, because some registers are banked (each mode has its own private copy).

Register banking

Counting: R0 to R7 (8) plus R8 to R12 (5 User + 5 FIQ = 10) plus R13 (6) plus R14 (6) plus R15 (1) = 31 general-purpose registers. Add CPSR and 5 SPSRs (6 status registers) to get 37.

CPSR layout

7. Processor Modes

Classic ARM (ARM7TDMI, ARM9) has 7 modes. User mode is unprivileged. The other six are privileged. Five of them are entered by exceptions, and System mode is entered by software.

• User mode cannot change the CPSR mode bits directly. A privileged mode or an exception is needed to switch modes.
• System mode has no registers of its own. It shares User-mode registers but runs with full privilege, which is useful for operating-system tasks.
• The five exception modes are FIQ, IRQ, Supervisor, Abort and Undefined.

8. Exceptions and the Vector Table

An exception is any event that interrupts normal program flow: a reset, an interrupt, a fault or a software interrupt. In classic ARM, the vector table starts at address 0x00000000. Each entry is 4 bytes, normally holding a branch instruction to the handler. Some cores can relocate the table to 0xFFFF0000.

Priority order, highest to lowest: Reset, Data Abort, FIQ, IRQ, Prefetch Abort, then SWI and Undefined Instruction (these two cannot occur together).

What the processor does when an exception occurs

1. Copies the CPSR into the SPSR of the new mode
2. Switches to the exception's mode by changing the CPSR mode bits
3. Switches to ARM state (T bit = 0)
4. Disables IRQ by setting the I bit (and also FIQ by setting the F bit for Reset and FIQ)
5. Stores the return address in the new mode's LR
6. Loads the PC with the vector address

Returning from an exception

The handler must restore the CPSR from the SPSR and the PC from the adjusted LR. Because of pipeline effects, the stored LR needs an offset:

The S suffix with PC as the destination copies the SPSR back to the CPSR, which restores the mode and flags automatically.

9. The ARM Pipeline

A pipeline overlaps the stages of consecutive instructions so that, ideally, one instruction completes every cycle.

• PC value: in a 3-stage pipeline, when an instruction is executing, the PC already points 2 instructions ahead. In ARM state, reading the PC therefore gives the address of the current instruction + 8. In Thumb state it is + 4.
• Branch penalty: a taken branch flushes the pipeline, which then has to refill. This is one reason ARM's conditional execution is valuable, since it avoids branches.
• Memory architecture: ARM7 is Von Neumann (one bus). ARM9 and later use a Harvard arrangement with separate instruction and data caches or buses.

10. ARM, Thumb, Thumb-2 and Jazelle

Switching between ARM and Thumb

• Use the BX (Branch and Exchange) instruction.
• Bit 0 of the target address decides the state: 1 means Thumb, 0 means ARM.
• The processor records the current state in the T bit of the CPSR.
• Thumb is typically about 65% of ARM's size in code density terms, but ARM state runs faster when memory is 32 bits wide.

11. The ARM Instruction Set

11.1 Instruction categories

• Data processing: AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV, BIC, MVN
• Multiply: MUL, MLA, UMULL, UMLAL, SMULL, SMLAL
• Load/store: LDR, STR, LDRB, STRB, LDRH, STRH, LDRSB, LDRSH
• Block transfer: LDM, STM
• Branch: B, BL, BX
• Status register transfer: MRS, MSR
• Exception generating: SWI (now called SVC)
• Swap: SWP (older cores)
• Coprocessor: CDP, LDC, STC, MRC, MCR

11.2 Data processing instruction format

Syntax: OPCODE{cond}{S} Rd, Rn, Operand2

• Bits 31 to 28: condition field
• Bit 25: I (1 means Operand2 is an immediate)
• Bits 24 to 21: opcode
• Bit 20: S (update the flags)
• Bits 19 to 16: Rn (first source)
• Bits 15 to 12: Rd (destination)
• Bits 11 to 0: Operand2

• TST, TEQ, CMP and CMN always update the flags and never store a result.
• MOV and MVN have no first operand (Rn).
• For other instructions, flags change only if you add the S suffix: ADDS, SUBS.

11.3 Conditional execution

The top 4 bits of every ARM-state instruction hold a condition. The instruction executes only if the condition is true; otherwise it acts as a no-op.

11.4 The barrel shifter

The second operand can be shifted or rotated before use, all inside one instruction:

• LSL: logical shift left
• LSR: logical shift right
• ASR: arithmetic shift right (keeps the sign bit)
• ROR: rotate right
• RRX: rotate right by one bit through the carry flag

ADD R0, R1, R2, LSL #2    ; R0 = R1 + (R2 << 2), i.e. R1 + 4*R2
MOV R3, R3, LSR #1        ; R3 = R3 / 2 (unsigned)

Immediate values: an immediate is encoded as an 8-bit number rotated right by an even number of bits. So MOV R0, #0xFF000000 is valid (0xFF rotated), but MOV R0, #0x101 is not, because its set bits span more than 8 bit positions. For arbitrary constants use the pseudo-instruction LDR R0, =0x101.

11.5 Load and store

LDR  R0, [R1]          ; R0 = word at address in R1
STR  R0, [R1, #4]      ; store R0 at R1 + 4 (offset addressing)
LDR  R0, [R1, #4]!     ; pre-indexed: R1 = R1 + 4, then load from R1
LDR  R0, [R1], #4      ; post-indexed: load from R1, then R1 = R1 + 4
LDRB R0, [R1]          ; load one byte (zero-extended)
STRH R0, [R1]          ; store a halfword

The three addressing styles are offset (base unchanged), pre-indexed (written with !, base updated first) and post-indexed (base updated after the access).

11.6 Load/store multiple and the stack

STM and LDM transfer several registers at once. The suffixes IA, IB, DA and DB mean Increment/Decrement, After/Before. For stacks, ARM's standard convention is Full Descending (FD): the stack grows toward lower addresses and SP points to the last item pushed.

STMFD SP!, {R0-R3, LR}   ; push (same as STMDB SP!, {R0-R3, LR})
LDMFD SP!, {R0-R3, PC}   ; pop and return (same as LDMIA SP!, {...})

In Thumb-2 code you will see the simpler PUSH and POP forms.

11.7 Branches

• B label: branch. The 24-bit signed offset (shifted left by 2) gives a range of about ±32 MB.
• BL label: branch with link. It copies the return address into LR, used for subroutine calls.
• BX Rm: branch and exchange, which can also switch between ARM and Thumb.
• Return from a subroutine: MOV PC, LR or BX LR.

11.8 Multiply, status register and software interrupt

• MUL Rd, Rm, Rs: Rd = Rm × Rs (32-bit result)
• MLA Rd, Rm, Rs, Rn: Rd = Rm × Rs + Rn (multiply-accumulate)
• UMULL RdLo, RdHi, Rm, Rs: 64-bit unsigned multiply (SMULL for signed)
• MRS Rd, CPSR: read the status register; MSR CPSR_f, Rm: write it
• SWI #n (now SVC): enters Supervisor mode via vector 0x08. Operating systems use it for system calls.

12. Worked Examples

Example 1: Flags after an addition

ADDS R0, R1, R2     ; R1 = 0xFFFFFFFF, R2 = 0x00000001

Result: R0 = 0x00000000. Flags: Z = 1 (zero), C = 1 (carry out of bit 31), N = 0, V = 0. Signed, this is -1 + 1 = 0, so there is no overflow.

ADDS R0, R1, R2     ; R1 = 0x7FFFFFFF, R2 = 0x00000001

Result: R0 = 0x80000000. Flags: N = 1, V = 1 (two positives gave a negative), Z = 0, C = 0.

Example 2: Sum of numbers 1 to 10

        MOV  R0, #0        ; sum = 0
        MOV  R1, #10       ; counter = 10
loop    ADD  R0, R0, R1    ; sum = sum + counter
        SUBS R1, R1, #1    ; counter-- and update flags
        BNE  loop          ; repeat until counter = 0
        ; R0 now holds 55

Example 3: GCD using conditional execution

gcd     CMP   R0, R1        ; compare a and b
        SUBGT R0, R0, R1    ; if a > b: a = a - b
        SUBLT R1, R1, R0    ; if a < b: b = b - a
        BNE   gcd           ; repeat until a = b
        ; R0 = GCD

There is no if/else branching inside the loop. The conditions on SUB do the job, which is exactly why ARM code is compact and fast.

Example 4: Skeleton of an IRQ handler (classic ARM)

IRQ_Handler
        SUB   LR, LR, #4            ; adjust return address
        STMFD SP!, {R0-R3, LR}      ; save registers
        ; ... service the interrupt ...
        LDMFD SP!, {R0-R3, PC}^     ; restore and return

The ^ after the register list tells the processor to copy the SPSR into the CPSR when the PC is loaded. This restores the flags and the mode in one step.

13. Memory, I/O and Buses

• Address space: 32-bit addresses give 4 GB of byte-addressable memory.
• Data types: byte (8-bit), halfword (16-bit) and word (32-bit). Words should be aligned to 4-byte boundaries and halfwords to 2-byte boundaries.
• Endianness: ARM supports both little-endian and big-endian, and is little-endian in most devices.
• I/O: memory-mapped only. Peripheral registers sit at fixed addresses and are read and written with LDR and STR.

AMBA bus standard

AMBA (Advanced Microcontroller Bus Architecture) is ARM's on-chip bus standard for connecting the CPU, memory and peripherals.

• AHB (Advanced High-performance Bus): fast bus for the CPU, DMA and memory
• APB (Advanced Peripheral Bus): simple, low-power bus for slow peripherals such as UART, timers and GPIO
• AXI (Advanced eXtensible Interface): high-performance interface used in Cortex-A and larger systems

Debug

ARM supports JTAG and the 2-pin Serial Wire Debug (SWD), along with the CoreSight debug architecture.

14. Cortex-M in Depth

Cortex-M cores are what you will find in most modern microcontrollers, and they differ from classic ARM in important ways.

Cortex-M family at a glance

Registers (Cortex-M3/M4)

• R0 to R12: general-purpose (R0 to R7 are "low" registers, R8 to R12 "high")
• R13: two stack pointers, MSP (Main Stack Pointer) and PSP (Process Stack Pointer), only one visible at a time
• R14 (LR) and R15 (PC)
• xPSR: combines APSR (flags N, Z, C, V, Q), IPSR (current exception number) and EPSR
• Special registers: PRIMASK (masks all configurable exceptions), FAULTMASK, BASEPRI (masks priorities at or below a level) and CONTROL

Modes and privilege

• Thread mode: runs normal application code, entered after reset
• Handler mode: runs exception handlers and is always privileged
• Thread mode can be privileged or unprivileged, selected by the CONTROL register

Note the contrast: classic ARM has 7 modes; Cortex-M has just 2 modes (plus privilege levels).

NVIC and the vector table

The NVIC (Nested Vectored Interrupt Controller) is built into the core. It supports nested interrupts, programmable priorities (a lower number means higher priority), and directly vectored handlers. Unlike classic ARM, the vector table holds handler addresses, not branch instructions, and it starts with the initial stack pointer value.

• Automatic stacking: on exception entry the hardware pushes 8 registers (R0, R1, R2, R3, R12, LR, PC and xPSR) onto the stack. The handler can therefore be an ordinary C function.
• Exception return: loading a special value called EXC_RETURN (such as 0xFFFFFFF9 or 0xFFFFFFFD) into the PC, usually with BX LR, triggers the return and the unstacking.
• Interrupt latency: 12 cycles on Cortex-M3 with zero-wait-state memory.
• Tail-chaining: when another interrupt is pending as one finishes, the core skips the unstack and restack steps and jumps straight to the next handler.
• SysTick: a built-in 24-bit down-counter timer, often used for the operating-system tick.

Memory map (Cortex-M3/M4)

Bit-banding lets you read or write a single bit with a normal word access. The first 1 MB of SRAM (0x20000000) is aliased into a 32 MB region starting at 0x22000000, and the first 1 MB of the peripheral region (0x40000000) into 0x42000000. Each bit gets its own word address, which makes bit operations atomic.

The Cortex-M3 uses a Harvard-style bus structure with separate instruction (I-Code) and data (D-Code) buses, plus a system bus.

15. 64-bit ARM: ARMv8-A and AArch64

• Execution states: AArch64 (64-bit) and AArch32 (32-bit, backward compatible)
• Registers in AArch64: 31 general-purpose 64-bit registers, X0 to X30 (the 32-bit views are W0 to W30), plus a dedicated stack pointer and a zero register (XZR/WZR)
• Instruction set in AArch64: new fixed 32-bit A64 instruction set
• Exception levels: EL0 (applications), EL1 (operating system), EL2 (hypervisor) and EL3 (secure monitor)
• Use: modern smartphones, laptops, servers and 64-bit embedded systems

16. ARM vs 8085, 8086 and 8051

Examiners love comparison questions across the microprocessors in this syllabus.

17. Where ARM Is Used, Especially in Telecom

• Mobile phones and tablets: application processors and cellular baseband modems
• Networking and telecom equipment: routers, modems, switches, small cells and base-station control boards
• IoT and wearables: sensors, smart meters, trackers (mostly Cortex-M)
• Automotive: infotainment, ADAS and engine control (Cortex-A and Cortex-R)
• Single-board computers: Raspberry Pi and similar
• Laptops and servers: 64-bit ARM chips are increasingly common

18. Common Exam Traps

19. Practice: 30 Exam-Style MCQs

Try each question first, then check the answer.

1. What does ARM stand for? Ans: Advanced RISC Machines (originally Acorn RISC Machine).
2. ARM is based on which architecture style? Ans: RISC, load/store architecture.
3. How many registers are visible at one time in ARM state (excluding the CPSR)? Ans: 16 (R0 to R15).
4. Which register is the Program Counter? Ans: R15.
5. Which register is the Stack Pointer? Ans: R13.
6. Which register holds the return address for BL? Ans: R14, the Link Register.
7. How many processor modes does ARM7TDMI have? Ans: 7 (User, FIQ, IRQ, Supervisor, Abort, Undefined, System).
8. Which is the only unprivileged mode? Ans: User mode.
9. Which mode has the most banked registers? Ans: FIQ (R8 to R14 plus SPSR).
10. What does the "T" in ARM7TDMI stand for? Ans: Thumb.
11. What does the "I" in ARM7TDMI stand for? Ans: Embedded ICE (in-circuit emulation).
12. How many pipeline stages does ARM7TDMI have? Ans: 3 (fetch, decode, execute).
13. How many pipeline stages does ARM9 have? Ans: 5.
14. What is the width of a Thumb instruction? Ans: 16 bits.
15. Which CPSR bit indicates Thumb state? Ans: The T bit (bit 5).
16. Which instruction switches between ARM and Thumb state? Ans: BX.
17. What is the width of the condition field in an ARM instruction? Ans: 4 bits.
18. What is the vector address of the IRQ exception in classic ARM? Ans: 0x00000018.
19. What is the vector address of FIQ? Ans: 0x0000001C.
20. Which exception has the highest priority? Ans: Reset.
21. Which ARM mode is entered on a software interrupt (SWI)? Ans: Supervisor mode.
22. Which instruction performs a subroutine call? Ans: BL (branch with link).
23. Which instruction compares two registers without storing a result? Ans: CMP (it sets the flags from Rn - Op2).
24. After SUBS with no borrow, what is the C flag? Ans: C = 1.
25. In ARM state, executing the instruction at address X, what does the PC read as? Ans: X + 8.
26. Which Cortex profile is aimed at microcontrollers? Ans: Cortex-M.
27. Which instruction set do Cortex-M3 cores use? Ans: Thumb-2 only.
28. What does the first word of a Cortex-M vector table contain? Ans: The initial Main Stack Pointer value.
29. How wide is the SysTick counter? Ans: 24 bits.
30. What is Arm's main business model? Ans: Licensing processor designs (IP) to chip makers.

20. One-Page Revision Cheat Sheet

Frequently Asked Questions

Is ARM in the JKSSB SI Telecom syllabus?

Yes. The syllabus lists "8051 microcontroller & Introduction to ARM" under Digital Electronics & Microprocessors, a 20-mark subject.

How deep should I study ARM for this exam?

Cover the concepts in this guide thoroughly: features, registers, modes, exceptions, pipeline, Thumb and the Cortex families. Detailed assembly programming is far less likely than direct factual questions.

Is ARM a microprocessor or a microcontroller?

ARM is a processor architecture and core design. Chip makers combine ARM cores with memory and peripherals to make microcontrollers (for example Cortex-M devices) or larger systems-on-chip (Cortex-A devices).

Always cross-check the syllabus and exam pattern against the official notification (Advertisement No. 11 of 2025) at jkssb.nic.in.